Upgrading the memory of the HP 42S to 32KB
Takayuki HOSODA
Oct. 10, 2007
hp42s-0.jpg

Japanese Japanese edition is here.


Top view Bottom view,
Battery cover removed
Four heat stakes and a
thin plate drill (3.8mm)
Cut out 1.5mm of the
top of the heat stakes
hp42s-2.jpg hp42s-3.jpg hp42s-4.jpg hp42s-5.jpg
Top end freed Front and back apart,
four hidden heat stakes
Back plate and a buzzer Print Circuit Board,
MPU with an SRAM
hp42s-6.jpg hp42s-7.jpg hp42s-8.jpg hp42s-9.jpg
Close up view of the
SRAM and the ROM pads
Remove the 8KB SRAM Change the jumpers then install a 32KB SRAM,
Remove fulx residue and make it clean
hp42s-10.jpg hp42s-11.jpg hp42s-12.jpg The original 8KB SRAM
S-MOS system's
SRM2264LM10
  Isb(typ) = 0.5μA
  Isb(max) = 20μA
was replaced with the 32KB
low power SRAM in a
standard 28-pin narrow
(300mil) SOIC package.
What I used here is
Cypress's
CY62256LL-70SNC
  Isb(typ) = 0.1μA
  Isb(max) = 5.0μA
Available Memory:
31533 Bytes

(firmware revision C)
Appendix 1 *note1
Buffered clock waveform
fclock = 32.768kHz
Appendix 2 *note2
Vdd noise at SRAM and
SRAM _WR waveform
Appendix 3 *note3, *note13
Replace solid tantalum
capacitors by multilayer
ceramic capacitors
hp42s-13.jpg hp42s-14.jpg hp42s-16.jpg hp42s-17.jpg
SN=3242S09191

*note1 : Clock frequency
There is a testpoint next to the crystal that seems to be
a buffered output of the clock oscillator.
The photo is the waveform of that point showing its frequency of
32.78kHz (actually 32.768kHz measured by a frequency counter).
*note2 : Noise and waveform
These waveform were measured while executing the test program shown below.
The Vdd noise at SRAM is acceptable and the RAM_WR waveform is not so bad.

00 { 15-Byte Prgm }
01 LBL "W"
02 STO "C"
03 CLX
04 RCL "C"
05 GTO "W"
06 .END.
*note3 : Capacitor replacement (Optional)
By replacing these solid tantalum capacitors to multilayer ceramic capacitors,
you can reduce its leakage current and also improve its life and reliability.
The larger 100μF/6.3V capacitor is used as the power supply decoupling, and
the other 10μF/16V capacitor is used as the filter of the voltage step up converter for LCD.
The capacitors that I used here are brandnew, high performance capacitors from
TDK (part code are shown below), so they are rather expensive yet. Notice that the
original part pads do just fit to these C3225 size capacitors by a very narrow margin.

TDK C3225(EIA CC1210) 100μF±20%/6.3V C3225JB0J107M
TDK C3225(EIA CC1210) 10μF±20%/16V C3225JB1C106M

The Vdd noise at SRAM is not reduced so much by this capacitor replacement,
as it's not intended. You can add 100nF to 1μF MLCC capacitor on the pads
between RAM and the processor for its power supply decoupling.
*note4 : Power supply current (fclock=32.768kHz, Vbattery=4.70V(SR44×3), Ta=26°C)
Irun ≈ 3.3mA
Iidle ≈ 380μA
Istandby ≈ 8.9μA

standby current monitor resistor standby current monitor resistor (1kΩ±0.05%//10μF±20%)
*note5 : Nominal capacity of SR44 is 165mAh.


Crystal resonator replacement for double speed 42S
Takayuki HOSODA
Jan. 08, 2008

Remove the original
32.768kHz crystal resonator
Install a 65.536kHz
crystal resonator
Original clock waveform
clock (above) and
SRAM_WR (below)
Modified clock waveform
clock (above) and
SRAM_WR (below)
hp42s-a.jpg hp42s-b.jpg hp42s-c.jpg hp42s-d.jpg
SN=3242S09191

Self-test result was OK, and the results of a user program which solves some transmission line parameters were as might be expected.

With setting the speed register at 0x40300 to 0xF by using the built-in debugger,
this modified 42S was able to execute the user program without error at quadruple speed of the original 42S with fresh batteries.

Self-Diagnositic-test ([EXIT]+[LN]) results at various frequency and voltage (Ta=27°C)
Ta=27°COscillator frequency [kHz] Comment
Vbattery65.536100.000131.072
4.7VO.K.O.K. O.K.Nominal voltage of SR44×3 at 20°C
3.8VCut-off voltage of SR44×3 at -10°C
3.7VROM O.K.
DRAM FAIL
URAM O.K.
ROM O.K.
DRAM FAIL
URAM O.K.
-
3.4V
3.0V
cann't turn oncann't turn on Low battery indicator turns on when
Vbattery ≤ 3.0V
2.9V
2.8V
ROM O.K.
DRAM FAIL
URAM O.K.
2.7V
Cut-off voltage of LR44×3 at 20°C

*note6 : Power supply current (fclock=65.536kHz, *(0x40300)==0x7, Vbattery=4.72V(SR44×3), Ta=24°C, SN=3242S09191 )
Irun ≈ 5.3mA
Iidle ≈ 440μA(typ.) (420μA/minimum contrast ~ 560μA/maximum contrast)
Iidle ≈ 440μA(typ.) (420μA/minimum contrast ~ 520μA/maximum contrast, Diode=BAR43CFILM)
Istandby ≈ 15 μA
Istandby ≈ 14.9 μA (Diode=BAR43CFILM)
Isleep ≤ 100 nA *note15
*note7 : Power supply current (fclock=65.536kHz, *(0x40300)==0xF, Vbattery=4.71V(SR44×3), Ta=23°C, SN=3242S09191 )
Irun ≈ 7.6mA
Iidle ≈ 480μA(typ.)

*note8 : Calculator Benchmark (N-queen problem) results
y:8
x:876

6:07.5 [min:sec] HP 42S (Rev.C) Keystroke / RPN / fosc=65.536kHz
3:28.0 [min:sec] HP 42S (Rev.C) Keystroke / RPN / fosc=65.536kHz / fast mode

*note9 : Weight
136.0g + 6.6g (batteries)

Modification on the earlier model of the 42S
Takayuki HOSODA
Jan. 20, 2008

I've done the same modification shown above on the other earlier model of the 42S (firmware revision A).
It works fine at the double speed, but was unable to be set to the "fast mode", so far. and also can be set to the fast mode without problem.

Rear view of the PCB
(firmware revision A)
Rear view of the LCD

Blow canned compressed gas
(HFC134a) to remove dust
within the LCD assembly
Top view of the PCB
after the modification
Back plate insulation
Kanton® tape applied*note13
hp42s-e.jpg hp42s-f.jpg hp42s-i.jpg hp42s-g.jpg hp42s-h.jpg
SN=3005S02826

The parts used for this modification are: *note10 : Power supply current (fclock=65.536kHz, *(0x40300)==0x7, Vbattery=4.73V(SR44×3), Ta=24°C)
Irun ≈ 5.0mA
Iidle ≈ 440μA(typ.) (400μA/minimum contrast ~ 540μA/maximum contrast)
Iidle ≈ 380μA(typ.) (340μA/minimum contrast ~ 420μA/maximum contrast, Diode=BAR43CFILM)
Istandby ≈ 14 μA
Istandby ≈ 13.5 μA (Diode=BAR43CFILM)
Isleep ≤ 100 nA
*note11 : Power supply current (fclock=65.536kHz, *(0x40300)==0xf, Vbattery=4.50V(SR44×3), Ta=22°C)
Irun ≈ 6.8mA
Iidle ≈ 440μA(typ.)
*note12 : Calculator Benchmark (N-queen problem) results
y:8
x:876

5:48.2 [min:sec] HP-42s (Rev.A) Keystroke / RPN / fosc=65.536kHz
3:30.4 [min:sec] HP-42s (Rev.A) Keystroke / RPN / fosc=65.536kHz / fast mode
*note13 : Apply Kapton® tape to the back plate
If you have replaced the 100μF solid tantalum capacitor with MLCC capacitors,
tough insulation tape such as Kapton® tape should be applied on the backplate upon the capacitors to avoid accidental short circuit.

*note14 : Weight
139.5g + 6.6g(batteries)
*note15 : Deep sleep mode
Press [EXIT], [+] and [XEQ] simultaneously to put it into deep sleep mode.

HP 42S partial schematic (Connections to the LCD are omitted)
Nov. 13, 2009
Takayuki HOSODA
Open fullsized schematic (27KB png)
HP 42S schematic

Rev.0.16 : Jan. 30, 2010
Rev.0.15 : Jan. 27, 2010
Rev.0.14 : Dec. 22, 2009

Membrane switch transplantation to repair the dead key switch of the HP-42S
Takayuki HOSODA
Nov. 17, 2009

Dead membrane switches After transplantation of
the membrane switches
The donor and acceptor
dead key switch after transplantation donor and acceptor
(→SN=2942S30206)


A work-around for sticking-to-low-contrast LCD problem of the HP-42S
Takayuki HOSODA
Jan. 23, 2010
LCD contrast

The sticking-to-low-contrast LCD problem, caused by broken switching transistor in the processor, was solved by using voltage doubler circuit instead.
For that purpose, the oscillator monitor output is used as its power source.

Modified LCD bias voltage generator Modified part of the PCB Voltage waveforms
Schematic PCB mod. waveform
SN=2942S30206 (The housing was exchanged for the one of the 42s that the key-switch was repaired before.)

  • The parts used for this modification, including SRAM and crystal resonator replacement, are: *note16 : Power supply current (fclock=65.536kHz, *(0x40300)==0xF, Vbattery=4.70V(SR44×3), Ta=25°C)
    Iidle ≈ 450μA(typ.) (440μA/minimum contrast ~ 550μA/maximum contrast)
    Istandby ≈ 22 μA
    Isleep ≈ 660 nA


    Double speed HP 42S with 32KB of nonvolatile RAM
    Takayuki HOSODA
    Dec. 10, 2013
    hp42s NV internal
    Thanks to the latest Ferroelectric Nonvolatile RAM from Cypress/Ramtron, which has wide supply voltage range of 2.7-5.5V, high endurance of 1014 read/writes, 38 year data retention and 20μA standby current, I was able to make the memory of an HP 42S nonvolatile. To utilize the NV-RAM FM18W08, slight modification is required to match the chip enable signal to that of the NV-RAM. As the *CE signal of the NV-RAM is used to latch the address value, the *CS1 from the processor must be gated by the address strobe (i.e. *CE = *CS1 & AS).
    Bus control signal waveforms of an hp42S
    hp42s *CS/AS
    ch1:*CS, ch2:AS (2V/div, 1μ/s, Vdd=4.2V, Ta=25°C)

    PCB modification for the nonvolatile RAM
    Wiring and decoupling capacitors
    hp42s NV PCB
    Close-up view of the FRAM(FM18W08-SG)
    hp42s NV FM18W08
    Close-up view of the multiple function gate (SN74LVC1G97)
    hp42s NV SN74LVC1G97
    SN=3005S02826
    hp42s/NV-RAM schematic diagram
    Click to open fullsized schematic (43KB gif)
    hp42s NV schematic
    Rev.0.19 : Dec. 11, 2013

    The parts used for this modification are: Results
    The HP 42S/NV keep working untill supply voltage drop down to 2.9V.
    The contents of the calculator survived the conditions below,
    *note17 : Power supply current (fclock=65.536kHz, Vbattery=4.70V(SR44×3), Ta=25°C, SN=3005S02826/FM28W08-SGTR)
    Irun ≈ 3.97mA
    Iidle ≈ 445μA
    Istandby ≈ 31.7μA
    Isleep ≈ 17.5μA
    *note18 : Power supply current (fclock=65.536kHz, Vbattery=4.70V(SR44×3), Ta=25°C, SN=3242S09191/FM28W08-SGTR)
    Irun ≈ 4.13mA
    Iidle ≈ 476μA
    Istandby ≈ 22.84μA
    Isleep ≈ 7.52μA

    The other way to make an HP 42S nonvolatile
    Takayuki HOSODA
    Dec. 15, 2013

    For an HP 42S which can operate at low battery voltage down to 3.0V, you can make use of a latest low voltage nonvolatile FRAM with address transient detector (e.g. Cypress/Ramtron's FM28V020) with 3.3V low-dropout voltage regulator. The FRAM don't need *CE control to latch the address, at the expence of relatively high standby current of 90μA. Together with 45μA of quiescent current of the LDO regulator, the standy current sums up to 135μA or more. Which means a set of new SR44 batteries won't last more than 50 days even at sleep mode. Therefore this modification is not recommended for actual use.

    PCB modification for the nonvolatile RAM
    A pullup resistor at *CE pin of FRAM is needed to keep the pin high during power cycles assuming the processor pin tri-states during the reset condition.

    FRAM, an LDO regulator, decoupling capacitors and a pullup resistor
    hp42s VR PCB
    SN=2909S32377
    hp42s/NV-RAM/LDO schematic diagram
    Click to open fullsized schematic (43KB gif)
    hp42s VR schematic
    Rev.0.19x : Dec. 15, 2013
    *note19 : Power supply current (fclock=65.536kHz, Vbattery=4.70V(SR44×3), Vcc=3.30V, Ta=25°C)
    Isleep ≈ 133μA
    DISCLAIMER
    These modifications are experimental, and the results should not be considered guranteed. The descriptions of the modifications herein does not imply endorsement or recommendation by the author.


    REFERENCE
    MoHPC HP Articles Forum, Increasing HP-42S Memory to 32K, Paul J. Brogger
    MoHPC HP Articles Forum, Pioneer keyboard schematic, Randy Slayer
    SEE ALSO
    HP Pioneer series calculator internals
    HP-27S LCD transplantation
    APPENDIX - Program library

    External LINKS
    Hewlett-Packard Calculator - Eric's site
    www.finseth.com - HPDATAbase
    www.hp42s.com - Home on the net for everything HP-42S
    www.hpmuseum.org - The Museum of HP Calculators
    MoHPC HP Articles Forum, Pioneer "Observational Internals", Paul J. Brogger
    MoHPC HP Articles Forum, HP-42S: New Facts, J-F Garnier
    HP-42S Fast Mode under program control, Gene

    Cypress
    TDK
    Maxell

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